architecture note

Pentium and PowerPC

The Pentium series is an excellent example of Complex Instruction Set Computer (CISC) design. The PowerPC is a direct descendant of IBM 801, one of the best designed RISC systems on the market.

Pentium

Intel has ranked the number one maker of microprocessors for decades. Here is a brief history of the evolution of microprocessors that Intel has been manufacturing.

PowerPC

In 1975, IBM started the 801 minicomputer project that launched the RISC movement. In 1986, IBM developed a RISC workstation, the RT PC, which was not a commercial success. In 1990, introduced the RISC/6000 and marketed that as a high performance workstation. IBM began to refer to this as the POWER architecture.

IBM then entered into an alliance with Motorola the developer of the 68000 series for Apple computers. The result of this alliance was the series of microprocessors that implement the PowerPC architecture. The processors in the series were: 601, 603, 604, 620, 740/750 (G3), G4, and G5. A complete description of the PowerPC ISA can be obtained from the IBM site.

Data Types

Pentium

• General - byte (8), word (16), doubleword (32), and quadword (64). signed integers are in 2's complement representation. Pentium uses little endian style representation.
• Floating point - single precision (32), double precision (64), extended double precision (80)
• BCD - unpacked (1 byte per digit) and packed (1 byte per 2 digits) representation

PowerPC

• General - byte (8), halfword (16), word (32), and double word (64). PowerPC can operate in little endian or big endian mode.
• Floating point - single precision (32), double precision (64)
• Byte string - 0 to 128 bytes in length

Registers

Pentium

• General - Eight 32 bit general purpose registers - EAX, EBX, ECX, EDX, ESP, EBP, ECI, and EDI. The low 16 bits of each of these registers act as 16 bit registers - AX, BX, CX, DX, SP, BP, CI, and DI. The lower and higher 8 bits of each of these 16 bit registers are also identified as registers - AL, BL, CL, DL, AH, BH, CH, and DH.
• Floating Point - Eight registers of 64 bit floating point numbers FP0 to FP7.
• Multimedia - Eight 64 bit multimedia registers MM0 to MM7.
• Segment - Six 16 bit segment selectors that index into segment tables - CS, SS, DS, ES, FS, and GS. CS register references the segment containing the instruction being executed. SS register references the segment containing the a user-visible stack. The remaining segment registers enable the user to reference upto four separate data segments at a time.
• Flags register contains condition codes and various mode bits.
• Instruction Pointer (IP) - address of the current instruction

PowerPC

• General: Thirty two 64 bit general purpose registers R0 to R31.
• Exception Register (XER): Reports exceptions in integer arithmetic operations.
• General: Thirty two 64 bit general purpose registers for all floating point operations FPR0 to FPR31.
• Floating point status and control register (FPSCR): 32-bit register that control the operation of floating point quantities.
• Condition register: Consists of eight 4-bit condition code fields.
• Link register: Used in conditional branch instruction and for call / return.
• Count: Used to control an iteration loop.

Addressing Modes

Pentium

• Immediate: Operand = A
• Register operand: LA = R
• Displacement: LA = (SR) + A
• Base: LA = (SR) + (B)
• Base with displacement: LA = (SR) + (B) + A
• Scaled index with displacement: LA = (SR) + (I) x S + A
• Base with index and displacement: LA = (SR) + (B) + (I) + A
• Base with scaled index and displacement: LA = (SR) + (I) x S + (B) + A
• Relative: LA = (PC) + a

where
LA = linear address
(X) = contents of X
SR = segment register
PC = program counter
A = contents of an address field in the instruction
R = register
B = base register
I = index register
S = scaling factor 

PowerPC

Load/Store Addressing

• Indirect: EA = (BR) + D
• Indirect indexed: EA = (BR) + (IR)

Branch Addressing

• Absolute EA = I
• Relative: EA = (PC) + 1
• Indirect: EA = (L / CR)

Fixed-point Computation

• Register: EA = GPR
• Immediate: Operand = I

Floating Point Computation

• Register: EA = FPR

where
EA = effective address
(X) = contents of X
BR = base register
IR = index register
L / CR = link or count register
GPR = general purpose register
FPR = floating point register
D = displacement
I = immediate value
PC = program counter 

Instruction Format

Pentium

This is a two address ISA, which means one of the source operands in some operations is also the destination. The length of the instruction is not fixed. It has a variable number of bytes.

• Instruction Prefix: Each instruction can have zero to four prefixes. The prefix overrides the ususal interpretation of the instruction.
• Opcode - one or two bytes
• ModR/m: This byte provide addressing information. The ModR/m byte specifies whether an operand is in a register or in memory.
• SIB: SIB byte specifies the full addressing mode. The SIB byte consists of three fields: The Scale field (2 bits) specifies the scale factor; the Index field (3 bits) specifies the index register; the Base field (3 bits) specifies the base register.
• Displacement: If the ModR/M specifies that the address calculation requires a displacement, the one, two, or four bytes is contained in the instruction.
• Immediate: Provides the value of an 8, 16, 32 bit operand.

PowerPC

All instructions in the PowerPC are 32 bits long and follow a regular format. The first 6 bits of an instruction specify the operation to be performed. For all load/store, arithmetic, and logical instructions, the up code is followed by two 5-bit register references, enabling 32 general purpose registers to be used.

Operations

Pentium

Data Movement

• MOV: Move operand between registers or between register and memory
• PUSH: Push operand onto stack
• PUSHA: Push all registers on stack
• MOVSX: Move byte, word, dword, sign extended
• LEA: Load effective address
• IN, OUT: Input, output operand from I/O space

Arithmetic

• ADD: Add operands
• SUB: Subtract operands
• MUL: Unsigned integer multiplication
• IDIV: Divide operands

Logical

• AND: And operands
• BTS: Bit test and set. The instruction copies the current value of a bit to flag CF and sets the original bit to 1
• BSF: Bit scan forward.Scans a word or dword for a 1-bit and stores the number of the first 1-bit into a register
• SHL / SHR: Shift logical left or right
• SAL / SAR: Shift arithmetic left or right
• ROL / ROR: Rotate left or right
• SETcc: Sets a byte to zero or one depending on any of the 16 conditions defined by status flags

Control Transfer

• JMP: Unconditional jump
• CALL: Transfer control to another location. The address of the next instruction following the CALL is placed on the stack
• JE / JZ: Jump if equal / zero
• LOOPE / LOOPZ: Loops if equal / zero. Conditional jump using a value stored in register ECX. The instruction first decrements ECX before testing ECX for the branch condition
• INT / INTO: Interrupt / Interrupt if overflow. Transfer control to an interrupt service routine

String Operations

• MOVS: Move byte, word, dword string. The instruction operates on one element of a string, indexed by registers ESI and EDI. After each string operation, the registers are automatically incremented or decremented to point to the next element of the string.
• LODS: Load byte, word, dword of string

PowerPC

Data Movement

• lwzu: Load word and zero extend to left; update source register
• ld: Load doubleword
• lmw: Load multiple word; load consecutive words into contiguous registers from the target register through general purpose register
• lswx: Load a string of bytes into registers beginning with target register; 4 bytes per register; wrap around from register 31 to register0

Arithmetic

• add: Add contents of two registers and place in third register
• subf: Subtract contents of two registers and place in third register
• mullw: Multiply low order 32 bit contents of two registers and place 64 bit product in third register
• divd: Divide 64-bit contents of two registers and place in quotient in third register
• lfs: Load 32 bit floating point number from memory, convert to 64 bit format, and store in floating point register
• fadd: Add contents of two registers and place in third register
• fmadd: Multiply contents of two registers, add the contents of a third, and place result in fourth register
• fcmpu: Compare two floating point operands and set condition bits

Logical

• cmp: Compare two operands and set four condition bits in the specified
• crand: Condition register AND: two bits of the Condition Register are ANDed and the resut placed in one of the two bit positions
• and: AND contents of two registers and place in third register
• cntlzd: Count number of consecutive 0 bits starting at bit zero in source register and place count in destination register
• rldic: Rotate left doubleword register, AND with mask, and store in destination register
• sld: Shift left bits in source register and store in destination register

Control

• b: Unconditional branch
• bl: branch to target address and place effective address of instruction following the branch into the Link Register
• bc: Branch conditional on Count Register and'or on bit in Condition Register
• sc: System call to invoke an operating system service
• trap: Compare two operands and invoke system trap handler if specified conditions are met